Keep platform-specific details in their guides, update the cross-links, and remove the release QA matrix link from the README.
91 lines
3.4 KiB
Markdown
91 lines
3.4 KiB
Markdown
# NVIDIA CUDA GPUs
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[README](../README.md) | [Getting started](../README.md#start-here)
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**Ada Lovelace is supported, including 48 GB L40S cards.** This is an important
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use case: a model whose other inference implementations require newer GPUs
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can still run here when DwarfStar supports its GGUF layout. The Flash kernels
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do not require Blackwell's native FP4 instructions; Ada uses an appropriate
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CUDA path. Support remains model-specific, not a promise to run arbitrary GGUFs.
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## Build
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Install the NVIDIA driver and CUDA toolkit, including `nvcc` and cuBLAS.
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Use the local GPU architecture, or select Ada explicitly:
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```sh
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make cuda-generic
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# For an Ada build:
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make cuda CUDA_ARCH=sm_89
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```
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For a GB10 machine use the [DGX Spark](DGX_SPARK.md) target instead.
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## Normal layer placement
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Without tensor parallelism, DwarfStar places complete layers on the selected
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GPUs. `--gpu-vram auto` uses reported free VRAM, reserving space for the graph
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and context. Explicit budgets are comma-separated GiB values, one per device.
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```sh
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./download_model.sh ds4f-q2
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./ds4 --cuda --gpu-devices 0,1,2,3 --gpu-vram auto --ctx 32768
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```
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This is also the multi-GPU placement mode for GLM. Startup refuses a layout
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that would require unsupported CPU execution; reduce context or choose a
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smaller model if necessary.
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## Flash tensor parallelism
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`--cuda-tensor-parallel` pairs GPUs and divides routed-expert work inside
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each pair. Pairs also own successive layer ranges. This is an in-process
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configuration, not the network `--role coordinator` / `--role worker` mode.
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The device order matters. List all layer-home GPUs first, then their partners.
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For physical pairs `(0,1)`, `(2,3)`, `(4,5)`, `(6,7)`, use:
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```text
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0,2,4,6,1,3,5,7
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```
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Check your machine's topology with `nvidia-smi topo -m`; do not assume this
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ordering gives the best pairs on another server. Each pair stores one half
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of the routed experts per GPU. Dense attention, routers, and shared experts
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are replicated within the pair; the output head is vocabulary-sharded.
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For the tested eight-L40S setup:
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```sh
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./download_model.sh ds4f-q4
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./ds4-agent --cuda --cuda-tensor-parallel \
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--gpu-devices 0,2,4,6,1,3,5,7 --gpu-vram auto --ctx 100000
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```
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Q4 has native grouped routed kernels for multi-user throughput. Q2 needs less
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memory, but unsupported grouped shapes use a slower, correct fallback.
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Four 48 GB cards with Q2 and eight with Q4 are tested configurations. An even
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device count alone does not guarantee memory fit.
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## Serve multiple users
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```sh
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./ds4-server --cuda --cuda-tensor-parallel \
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--gpu-devices 0,2,4,6,1,3,5,7 --gpu-vram auto \
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--ctx 100000 --batched-session 16 --host 0.0.0.0
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```
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The supported eight-L40S Flash configuration has reached roughly 126 aggregate
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generation tokens/s with 16 decode rows. This is total throughput, not the
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speed of one user. The recorded conditions and regression requirements are in
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[the QA guide](../QA_BEFORE_RELEASES.md).
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CUDA TP defaults to 2048-token prefill chunks. Keep that default for the
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16-session, 100k-context setup; larger chunks need more scratch memory.
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Reduce session count or context if all KV states do not fit.
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The repository's [server launcher](../run-nvidia-tp-server.sh) is an example
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from the L40S deployment, not a portable default: it uses host-specific model
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and cache paths and defaults to MXFP4. The commands above need no launcher or
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environment tuning. See [serving](SERVER.md) for disk caches and API access.
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